Timing analysis

Setup, hold, slack and corners in plain words, and what to do when timing is not met.

StudentEngineer 2 min read · Updated 2026-10-05

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        The ideaSetup and holdSlackCornersWhat sets the requirementWhen timing is not metIn the lab
      

A design is not finished when it works in simulation. It must also be fast enough to work on silicon, where every gate and wire takes time.

The idea#

Data leaves one flip-flop on a clock edge, passes through logic gates and wires, and must arrive at the next flip-flop before the next clock edge. The clock period is the time it has.

Data leaves on the launch edge, passes through the logic, and must be stable before the setup window of the capture edge and until the hold window closes. The spare time is the slack.

Setup and hold#

Setup. The data must arrive early enough before the clock edge. A setup problem means a path is too slow for the clock.
Hold. The data must stay steady for a moment after the clock edge. A hold problem means a path is too fast, and new data overwrites the old before it is captured.

Slack#

Slack is the margin a path has. Positive slack means the path meets its requirement with time to spare. Negative slack is a violation. The report gives the worst slack for setup and for hold.

Corners#

A chip does not behave the same in every condition. The build checks timing at several corners: combinations of manufacturing variation, voltage and temperature. Setup is usually hardest at the slowest corner, and hold at the fastest. A design meets timing only when every corner passes.

One path at three corners. Setup is checked where the chip is slowest, hold where it is fastest. An illustration of the idea, not measured values.

What sets the requirement#

Timing is judged against the constraints in force: the clock period in openlane/config.json, and the timing the flow applies at the inputs and outputs. Read the slack the report gives. Do not judge timing from the clock period alone.

When timing is not met#

Problem	What helps
Setup, a long chain of logic in one cycle	Split the work across two cycles with a register (a pipeline stage). This adds a cycle of latency, so the specification must allow it
Setup, a wide multiplier or adder	Reduce the width if the specification allows, or pipeline it
Hold	The tools try to repair hold problems themselves. Any that remain need a closer look. Slowing the clock does not fix a hold problem

In the lab#

The build card shows Timing met or Timing not met. The chip report has the numbers. When timing is not met, Nelix Agent can explain which path is the problem and suggest fixes drawn from the measured results.

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