Platform overview
The areas of the lab, the tabs of a project, where to find things, and the Lab map that shows it all on one page.
The lab has two kinds of place. The left sidebar takes you to the big areas: your projects, Autopilot, Design Chat, the Analog and Process Labs, Learn and these Docs. A project is your workbench: its tabs follow the road from an idea to a chip you can send to the fab.
Lab map in the sidebar, right under Docs, shows all of this on one page: the journey of a chip with the tab and button for every step, the sidebar, the project tabs, and a "Where do I find…" table.
The journey of one chip#
- Start a projectMy projects › New project, or Autopilot
- Write the RTLCode › Code editor
- SimulateOverview › Simulate, Code › Testbench
- SynthesizeOverview › Synthesize
- Build the chipRun all stages, Chip Layout
- Check itthe V&V tab, Open the chip report
- Share and shipResults & export, Project › Tapeout
Nelix Agent is there at every step: Ask Nelix Agent on every page and every V&V row, Chat in the project header, and Design Chat in the sidebar. It explains and suggests; the measured results of the tools always win.
The sidebar#
| Group | Entries |
|---|---|
| Top | New project |
| Lab | Home, Autopilot, My projects, Design Chat, Analog Lab, Process Lab, Get your chip made |
| Learn | Learn, Docs, Lab map (students in a class also see My classes) |
| University, Teaching | For university admins, professors and teachers: Overview, Classes, Teachers, Students, Usage & seats, Settings; Teaching home, Assignments |
| Bottom | Upgrade, Send feedback |
Your name at the top right opens Profile, Account (settings and the language Nelix Agent answers in), Plan, Team, Usage and Help.
A project's tabs#
Open a project from My projects. The header has Code editor, Terminal, Run all stages, Chat and ⋯. Under it are the tabs:
| Tab | What is in it |
|---|---|
| Overview | The road map: Write RTL, Simulate, Synthesize, Build the chip, Sign-off, Export, each step with its own buttons |
| Chip Layout | The picture of your chip, the 3D view and Design review |
| Code | Code editor, Terminal, Testbench, Fix a failed test |
| Runs & Compare | Runs, Compare, Compare snapshots, All runs |
| Results & export | Results, Artifacts, Cells, Share, Push to GitHub, Engineering details |
| V&V | Every check grouped by phase, with Open the chip report, See the violations on the chip and Tapeout readiness |
| Project ▾ | Design: Requirements, Module hierarchy, Version history. Check: Verification, Area, timing & power estimate. Build: Chip build settings, Versions & pinning. Share & ship: Review & sharing, Tapeout, Export / GitHub |
Where do I find…#
| I want to… | Go here |
|---|---|
| Read the full chip report | Open the chip report on the Overview, Results & export or V&V |
| See DRC or LVS errors on the layout | See the violations on the chip |
| Look at waveforms | Overview › Simulate, then the waveform; Fit to window and Full screen are at its top |
| Choose which test Simulate runs | Code › Testbench, "What Simulate runs" |
| Check that the chip can be taped out | Tapeout readiness on V&V, or Project ▾ › Tapeout |
| Download files or the GDS | Results & export › Artifacts |
| Change the process or the clock | Project ▾ › Chip build settings, then Run all stages |
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