Waveforms, reports and artefacts
Open the waveform, the schematic, the layout and the chip report, and read a run's log.
On this page
The waveformReading the MAC-8 waveformThe schematicThe layoutThe chip reportPush to GitHubA run's logEvery stage that passes gives you something to look at.
| Stage | Button | What you see |
|---|---|---|
| Simulate | See the waveform | Every signal in the design over the length of the test |
| Synthesize | See the schematic | The logic gates the design became |
| Build the chip | See the layout | The placed and routed chip |
| Build the chip | Open the chip report (and See the violations on the chip when a check found problems) | Measured timing, area, wire length and the checks that passed |
The waveform#
The waveform shows each signal as a row, with time running left to right. From the terminal, nelix waveform prints the address of the same viewer.
Fit to window shows the whole run and makes the viewer tall enough for every signal (up to the height of your browser window); Full screen puts the viewer on the whole screen with Fit, Show all signals and Exit full screen on top (Esc also leaves), and you can drag the bar at the bottom edge of the viewer to make it taller or shorter (this browser remembers the height).
Reading the MAC-8 waveform#
Follow the acc row. The test checks these totals; the waveform shows the same 20-bit value in hexadecimal.
| Step | Total | acc in hex |
|---|---|---|
| 3 x 4 | 12 | 0000c |
| add 5 x 6 | 42 | 0002a |
| add -2 x 7 | 28 | 0001c |
| add -3 x -5 | 43 | 0002b |
en low, inputs held | 43 | 0002b |
| add -128 x -128 | 16427 | 0402b |
| add 127 x -128 | 171 | 000ab |
rst_n low | 0 | 00000 |
Negative inputs appear as fe for -2 and fd for -3. With en low, acc holds its value. rst_n low clears it to 0.
Explain this waveform (where Nelix Agent is available to you) reads the real signals of the run and explains them. For a bus your design declares signed (for example logic signed [7:0] a), the values are shown as signed numbers with their raw bits: -2 (0xFE, signed), not 254.
acc is 12 after 3 x 4, then 42, 28 and 43. It holds 43 while en is low, and returns to 0 when rst_n goes low. Recorded from a real simulation.The schematic#
The schematic is drawn from the synthesized design. Boxes are registers, arithmetic, multiplexers and logic; lines are the nets between them. It is the quickest way to check that the tools understood your code the way you meant it.
Large designs (since 31 October 2026). A real design is a tree of modules, and the page shows it that way. The left side lists every module with its number of blocks; the drawing shows the module you chose, with its sub-modules as boxes you can click to step inside (the trail at the top takes you back up). A module with more than 400 blocks is too dense to draw as one picture, so the page says so, gives the count, and offers its sub-modules instead; nothing is hidden. Find a signal or block by typing part of its name: the matches light up and the rest fades. Save as image gives you the current view as SVG or PNG in the lab's dark style with the design's name, ready to post. The IDE command nelix schematic --module <name> draws one module as before. A design the lab had to prepare with the Slang reader (modern SystemVerilog the flow's own Yosys refuses) keeps its module tree as well (since 31 October 2026, evening): the elaboration is written module by module, and a module used several times appears once per instance, named <module>_<instance>.
$adff and $adffe), an adder ($add) that feeds the count back plus one, and a comparison ($eq) with 32 that drives done.The layout#
The layout viewer shows the finished chip. Rows of standard cells sit under layers of metal wiring. Zoom in to see individual cells; turn layers on and off to follow a wire. The layers carry the names of your design's process (for example Metal1 and Poly2 on GF180MCU, Activ and GatPoly on IHP SG13G2).
The chip report#
The report lists what the build measured: the number of cells, the die area, the timing margin at each corner, the wire length, and whether the layout checks passed. See Timing explained for how to read the timing lines.
The headline is about the checks that ran. When every check the lab ran for the process passed, the report says Available checks passed and lists what was not run for that process (for example the shuttle's own precheck, or GlobalFoundries' KLayout deck on GF180MCU, or the KLayout LVS cross-check on IHP SG13G2). A check that did not run is shown as Not run in this build, never as zero errors.
Results from before a change. If you change the design after a run, the Results page, the chip report, the Share page and the Tapeout page say Historical: the design changed after these results. The numbers stay readable, as they were measured on the earlier design; run the stages again to check the design as it is now.
The area numbers. The Area box names what each number counts. What each number counts under it explains them:
| Line | What it counts |
|---|---|
| Logic cell area | Flip-flops, gates, inverters and buffers: the cells that do the work |
| Placed cells, without fill | The logic cells plus tap, end-cap and antenna-diode cells |
| All placed cells, with fill | Also the filler and decap cells that close the gaps. They fill the core, so this can equal the core area |
| Core area | The part of the die where cells can be placed |
| Die area | The whole chip, with the ring for power and pins |
| Utilization | Placed cells without fill ÷ core area |
Max clock is an estimate from the setup slack: 1 ÷ (clock period − worst setup slack). Only the setup slack at the clock you set was measured.
Push to GitHub#
Results & export → Push to GitHub sends your project's source files to one of your own GitHub repositories as a single commit.
- On GitHub, make a fine-grained token that can write to that one repository.
- Paste it once. The lab keeps it locked and shows only its last 4 characters; Forget my token removes it.
- Check and show what will be pushed lists exactly which files would be sent: your design, tests and settings, never runs, logs or waveforms.
- Push … files to GitHub sends that list as one commit after you confirm. It never overwrites a branch that changed on GitHub since, and files already in the repository stay.
The History page also has a one-off push that uses a token for that push only and never saves it.
A run's log#
On the Runs page, open a run to read its log. The log shows where the run stopped. On a build, the useful line is the last real step, such as a layout comparison or a design-rule check.
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